1. Technical Field
Embodiments of the present disclosure may generally relate to semiconductor devices relating to correcting data errors and semiconductor systems including the same.
2. Related Art
Attempts to increase integration density in semiconductor devices have typically resulted in the increase of failed memory cells within the fabrication process of the semiconductor devices. This may lead to lowering the fabrication yield of the semiconductor devices. Even though each semiconductor device has a single defective memory cell, the semiconductor device cannot be supplied to customers.
A lot of effort has been focused on improving the fabrication yield of highly integrated semiconductor devices. For example, various techniques for repairing addresses of failed memory cells with redundancy memory cells have been proposed to improve the fabrication yield of these highly integrated semiconductor devices.
Recently, a DDR2 scheme or a DDR3 scheme receiving and outputting four bit data or eight bit data during each clock cycle time has been used to improve an operation speed of the semiconductor devices. If a data transmission speed of the semiconductor devices becomes faster, the probability of causing errors increases while the data is transmitted within the semiconductor devices. Accordingly, novel design schemes may be required to guarantee a reliable transmission of the data.
Whenever data is transmitted within a semiconductor device, error codes which are capable of detecting occurrence of errors may be generated and are then transmitted with the data to improve the reliability of data transmission. The error codes may include an error detection code (EDC) which is capable of detecting errors and an error correction code (ECC) which is capable of correcting the errors by itself.